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"University Research Journal" № 5, 2013 г.

Processor-Driven Emulated Upset-Like Fault Injection for Memory Validation

O. V. Mamoutova
Price: 50 руб.
Hardware emulated fault injection techniques on FPGA-based systems are widely used to validate reliability of designed circuits under SEU occurrence. Unlike simulation-based approaches, these techniques enable long-run experiments for observation of system reaction to upsets. Although most of these techniques target analysis of reaction to SEU in fl ip-fl ops, only few of them allow injection of upsets into embedded memories. In this paper, a new approach to implement fault injection for embedded memory is proposed, offering reduced hardware and time overhead. To control fault injection a distributed net of saboteurs should be connected to the processor of the analyzed system. Important circuit space savings can be achieved
as the processor acts as control logic for fault injection process. The fault injection environment is detailed, using OpenRISC1200 as an example, and experimental results are discussed.
Keywords: embedded memory, fault emulation, fault injection, FPGA, reliability
validation, SEU
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